An adder is a logic circuit that performs the addition of multi-bit binary numbers. Adders are one of the fundamental sub-units used in complex digital circuits such as, for example, an arithmetic logic unit in a central processing unit. Because adders are widely used, an increase in the processing speed of the adder may lead to a significant increase in the overall processing speed of the device of which the adder is a part.
When adding multi-bit binary numbers, the sum of any two bits may cause a carry that impacts the results at more significant bits. For this reason, an adder circuit must be designed to take into account ripple carrys that may occur. For example, the carry from the addition of the least significant input bits may be allowed to ripple across to logic that provides the most significant bits of the sum. A carry look-ahead adder is a type of fast adder that provides logic to permit the carry to propagate faster, with fewer number of gates, than having to ripple through each of the previous bit positions. As is known in the art, a carry look-ahead adder may include sub-circuits that provide intermediate values such as a generate value, a propagate value, and a carry value for different bit positions in the binary numbers being added. Such generate, propagate and carry values may then be used to provide the final sums bits. The logic for each bit position may be referred to as a “stage” of the adder.
In addition to processing speed, another design criteria considered is the complexity of the circuit. If the complexity of the circuit is increased, this may increase the design costs of the circuit as well as the cost of the circuit materials, the amount of area occupied by the circuit, and the cost to operate the circuit. Thus, there is an advantage to both reducing the processing speed and the complexity of the circuit. A technique used to reduce the complexity of a look-ahead carry adder circuit is to arrange the carry generation logic as units (“groups”) each of which receives a subset of the input bits and provides carry bits as outputs. In an embodiment, the carry generation block associated with a stage provides a carry value for use by the next stage. For example, assuming that the two addends are A and B, then the carry generation block associated with bits A0 and B0 provides a carry value C1. If the result of A0+B0 provides a carry, then C1=1. As would be appreciated by a person of skill in the art, a “value” received by (or output from) a gate is a voltage range that represents a logical value. In an embodiment, the carry generation block for each group provides one or more carry outputs which may be connected to one or more inputs of the carry generation block for the next group. For example, the inputs and logic may be grouped into units of four bits, with a carry output from the first group (e.g., the logic for bits 0-3) used as a carry input to the second group (e.g., the logic for bits 4-7), a carry outputs from the second group used a carry inputs to the third group, etc. In known look-ahead carry adders, the inputs (and corresponding logic) have been grouped in multiples of 2. For example, each group may have 2 bits. In other embodiments, each group contains 4 bits, each group contains 8 bits, etc.